Cadence SPB Allegro and OrCAD 17.40.000-2019 HF017
Cadence SPB Allegro and OrCAD 17.40.000-2019 HF017 | 5.6 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled a new of improvements in hotfix 017 to the Cadence SPB Allegro and OrCAD 17.40 families of products aimed at boosting performance and productivity through improvements features and big fixed issues.

CCRID Product ProductLevel2 Title

2293395 ALLEGRO_EDITOR 3D_CANVAS Improve quality of 3D export of JPEG/PNG images
2441565 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas: padstacks on edge of flex cutout that are partially milled away show floating in free space when using bend
2451128 ALLEGRO_EDITOR EDIT_ETCH Allegro PCB Editor crashes without any message while routing differential pair
2350433 ALLEGRO_EDITOR INTERFACES Allegro PCB Editor board geometry, Design_Outline produces incorrect outline in Export PDF drill drawing
2366356 ALLEGRO_EDITOR INTERFACES Export PDF does not export design outline as expected: PDF output has distorted outline
2399627 ALLEGRO_EDITOR INTERFACES File > Export > PDF not exporting property specified in the Property Parameters tab
2443075 ALLEGRO_EDITOR INTERFACES Extra lines are exported in PDF output
2441859 ALLEGRO_EDITOR IN_DESIGN_ANA Flex Zone returns no data for Impedance Workflow
2447640 ALLEGRO_EDITOR IN_DESIGN_ANA In-Design Analysis: Impedance analysis data not associated for Net segments that are part of flex zones
2448995 ALLEGRO_EDITOR IN_DESIGN_ANA Load Workflow does not work correctly on IR Drop.
2463485 ALLEGRO_EDITOR IN_DESIGN_ANA Aurora IR Drop SINK information not read from IDAX Workspace file
2429237 ALLEGRO_EDITOR NC Auto-generating tool file includes tool sizes for unused back drills in the padstack
2456751 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor drop-down menu unit changes even when canceled
2424319 ALLEGRO_EDITOR STEP Allegro PCB Editor crashes choosing Setup->Step Package Mapping in release 17.4-2019
2460486 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes: Artwork, NC Drill windows cannot be closed by clicking the ‘X’ button
2464932 ALLEGRO_EDITOR UI_FORMS No action after closing the "Select DXF Layer Conversion File" window and then clicking the Lib button
2469748 ALLEGRO_EDITOR UI_FORMS Command with form does not complete when closing forms using Cross button (X)
2471708 ALLEGRO_EDITOR UI_FORMS Right-click and "Done" required even after running scripts to do the same in release 17.4-2019
2453999 ALLEGRO_EDITOR UI_GENERAL Getting "Unsaved changes. Commit before exiting?" when trying to exit from a design
2434693 ALLEGRO_PROD_TOOLB CORE Productivity toolbox advanced cross-section generator issue – mirrored vias are shown upside down in the chart
2356991 ALLEGRO_VIEWER OTHER Unable to run Allegro Free Physical Viewer because orIPC64.dll is not present in release 17.40-2019
2254401 ALTM_TRANSLATOR CAPTURE OrCAD Capture stops responding when opening design translated from third-party: Large number of items in cache
2423347 ALTM_TRANSLATOR PCB_EDITOR Cannot import third-party design in OrCAD Capture
2437482 ALTM_TRANSLATOR PCB_EDITOR Third-party translator fails: Large extent and components not created but routing shows more than 90% connectivity
2423353 APD WIREBOND Realigning bond fingers to the Wire Bond Guide path using "Change Characteristics" does not work
2185806 CAPTURE SCHEMATIC_EDI Tooltip flickering issue: Tooltip flickers when hovering over large components
2444647 CONCEPT_HDL CORE Bill of Material is not running in DE-HDL.
2441376 CONSTRAINT_MGR CONCEPT_HDL Design Entry HDL ECSets marked as read-only
2322140 CONSTRAINT_MGR INTERACTIV Selecting Constraint Manager Spacing>Net Class-Class>CSet assignment matrix filtering icons causes crash
2359979 CONSTRAINT_MGR UI_FORMS CentOS 7.7: CM window and scroll bars not refreshing in release 17.4-2019
2433619 F2B PACKAGERXL Design Entry HDL PXL fails and causes restart because pxl.log cannot be found
2440978 ORBITIO ALLEGRO_SIP_I Die size imported from OrbitIO into APD Plus wrong: Scribe width calculated incorrectly
2457245 ORBITIO DEVICES TSV via array creation in OIO under cover, removes the wires after ungrouping
2437608 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues with new Symbol Editor and Part Developer
2451774 PCB_LIBRARIAN SYMBOL_EDITOR Cannot change pin number in property panel in new Symbol Editor
2443079 PSPICE TI_CONTRACT Libraries fail to update on some systems
2452925 PSPICE TI_CONTRACT The memory used by Capture increases abnormally when there are many libraries defined in PSpice.ini
2458644 PSPICE TI_CONTRACT PSpice and memory management: Memory increases abnormally
2437443 PULSE UNIFIED_SEARC Cannot search for components with ‘/’ in their names in QIR2 of release 17.4-2019
2438444 SYSTEM_CAPTURE DARK_THEME Difficult to read Variant Editor popup because of white text on white background
2452823 SYSTEM_CAPTURE REPLACE Allegro System Capture: Connections to ground symbols lost after installing release 17.4-2019, HotFix 015
2457647 SYSTEM_CAPTURE UI System Capture window positioning broken on changing from 2- or 3-screen docking station back to laptop or vice versa
2443661 SYSTEM_CAPTURE UNIFIED_SEARC Variant Editor crashes on choosing ‘Add Preferred’ or ‘Add Alternate’
2462568 SYSTEM_CAPTURE WIRING Cannot connect wire to pin
2435194 SYS_RELIABILITY SCH_AUDIT ‘Net UNNAMED_… is unconnected’ violation points to orphan object
2450477 TOPXP ALLEGRO_INTEG Topology Extraction does not support multi zone flex designs
2444806 TOPXP CHANNEL_SIMUL Topology Explorer serial link analysis reports incorrect baud rate
2450628 TOPXP CHANNEL_SIMUL Topology Explorer crashes when loading a topology with a redriver
2444712 TOPXP SYSTEMSI Running a Topology Explorer PBA analysis provides an error box with no error message.
2451503 TOPXP SYSTEMSI Maximum CPUs limited to 36 for circuit simulation
2459725 TOPXP SYSTEMSI EBD flags error on same memory devices
2453478 TOPXP TOPXPLORER Topology Explorer license chooser fails to present appropriate list of licenses and Reset Cache checkbox is not present.
Cadence OrCAD and Allegro 17.4-2019is a sleeker and more modern version of the OrCAD and Allegro release, with enhanced usability and a slew of new productivity- enhancing features. You get more intuitive and easy- to- use flows that enable optimized schematic- to- board- to- manufacturing transitions. So, whether you design schematics, work with physical layouts, manage or create libraries and parts, or administer ECAD processes, there are features in this release that will benefit you.
Starting with OrCAD and Cadence Allegro PCB – Tutorial for Beginners
Cadenceenables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product:Cadence SPB Allegro and OrCAD
Version:17.40.000-2019 HF017
Supported Architectures:x64
Website Home Page :http://www.cadence.com
Language:english
System Requirements:PC *
Software Prerequisites:Cadence SPB Allegro and OrCAD 17.40.000-2019 and above
Size:5.6 Gb

System Requirements:
OS:Windows 10 (64-bit) Professional, Windows Server 2012 (All Service Packs); Windows Server 2012 R2; Windows Server 2016.
CPU:Intel Core i7 4.30 GHz or AMD Ryzen 7 4.30 GHz with at least 4 cores
Memory:16 GB RAM
Space:50 GB free disk space (SSD drive is recommended)
Display:1920 x 1200 display resolution with true color (at least 32bit color)
GPU:A dedicated graphics card supporting OpenGL, minimum 2GB (with additional support for DX11 for 3D Canvas)
Monitors:Dual monitors (For physical design)
Supported MATLAB Version:R2019A-64Bit (For the PSpice-MATLAB interface)

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